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preliminary data january 2012 doc id 022570 rev 2 1/66 66 STA309B multichannel digital audio processor with ffx ? features 8 channels of 24-bit ffx ? >100 db snr and dynamic range selectable 32 kh-192 khz input sampling rates 6 channels of dsd/sacd and pdm input digital gain/attenuation +58 db to -100 db in 0.5 db steps advanced ?pop-free? operation digital ?pop-free? operation for single-ended mode soft volume update individual channel and master gain/attenuation plus channel trim (-10 db to +10 db) up to 10 independent 32-bit user- programmable biquads (eq) per channel bass/treble tone control pre- and post-eq full 8-channel input mix on all 8 channels dual independent limiters/compressors dynamic range compression or anti-clipping modes automodes ? 5-band graphic eq ? 32 preset eq curves (rock, jazz, pop, etc.) ? automatic volume controlled loudness ? 5.1 to 2-channel downmix ? simultaneous 5.1- and 2-channel downmix outputs ? 3 preset volume curves ? 2 preset anti-clipping modes ? preset movie nighttime listening mode ? preset tv channel/commercial agc mode ? 5.1, 2.1 bass management configurations ? am frequency automatic output pwm frequency shifting ? 8 preset crossover filters individual channel and master soft/hard mute automatic zero-detect and invalid input mute automatic amplifier powe r-down on clock loss advanced am interference frequency switching and noise suppression modes i 2 s output channel mapping function independent channel volume and dsp bypass channel mapping of any input to any processing/ffx channel selectable per-channel ffx damped ternary or binary pwm output max power correction fo r lower full-power thd variable per-channel ffx o utput delay control 192 khz internal processing sampling rate, 24-bit to 36-bit precision description the STA309B is a single-chip solution for digital audio processing and control in multichannel applications and provides output capabilities for ffx (full flexible amplific ation). in conjunction with an ffx power device, it provides high-quality, high-efficiency, all-digital amplification. the device is extremely versatile, allowing for input of most digital formats including 6.1/7.1-channel and 192 khz, 24-bit dvd-audio, dsd/sacd and pdm for mems microphone inputs. in the 5.1 application, the additional 2 channels can be used for audio line-out or headphone drive. in speaker mode, with 8 channel outputs in parallel, the STA309B can deliver 1 w (maximum). table 1. device summary order code package packaging STA309B vfqfpn56 tube STA309Btr vfqfpn56 tape and reel vfqfpn-56 www.st.com
contents STA309B 2/66 doc id 022570 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5i 2 c bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.2 multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2.1 configuration register a (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2.2 configuration register b (0x01) - serial input formats . . . . . . . . . . . . . . 24 7.2.3 configuration register c (0x02) - serial output formats . . . . . . . . . . . . . 26 7.2.4 configuration register d (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2.5 configuration register e (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2.6 configuration register f (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STA309B contents doc id 022570 rev 2 3/66 7.2.7 configuration register g (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2.8 configuration register h (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2.9 configuration register i (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2.10 master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.11 master volume register (0x0a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.12 channel 1 volume (0x0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.13 channel 2 volume (0x0c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.14 channel 3 volume (0x0d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.15 channel 4 volume (0x0e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.16 channel 5 volume (0x0f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.17 channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.18 channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.19 channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.20 channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 34 7.2.21 channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 34 7.2.22 channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 34 7.2.23 channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 35 7.2.24 channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 35 7.2.25 channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 35 7.2.26 channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 35 7.2.27 channel 8 volume trim, mute, bypass (0x1a) . . . . . . . . . . . . . . . . . . . . 35 7.2.28 channel input mapping channels 1 and 2 (0x1b) . . . . . . . . . . . . . . . . . 37 7.2.29 channel input mapping channels 3 and 4 (0x1c) . . . . . . . . . . . . . . . . . 37 7.2.30 channel input mapping channels 5 and 6 (0x1d) . . . . . . . . . . . . . . . . . 37 7.2.31 channel input mapping channels 7 and 8 (0x1e) . . . . . . . . . . . . . . . . . 37 7.2.32 auto1 - automodes eq, volume, gc (0x1f) . . . . . . . . . . . . . . . . . . . . 38 7.2.33 auto2 - automodes bass management2 (0x20) . . . . . . . . . . . . . . . . . 39 7.2.34 auto3 - automode am/pre-scale/bass management scale (0x21) . . . 40 7.2.35 preeq - preset eq settings (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2.36 ageq - graphic eq 80-hz band (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.37 bgeq - graphic eq 300-hz band (0x24) . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.38 cgeq - graphic eq 1-khz band (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.39 dgeq - graphic eq 3-khz band (0x26) . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.40 egeq - graphic eq 8-khz band (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.41 biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 43 7.2.42 mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 44 7.2.43 eq bypass (0x2a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
contents STA309B 4/66 doc id 022570 rev 2 7.2.44 tone control bypass (0x2b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2.45 tone control (0x2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.46 channel limiter select channels 1,2,3,4 (0x2d) . . . . . . . . . . . . . . . . . . . 45 7.2.47 channel limiter select channels 5,6,7,8 (0x2e) . . . . . . . . . . . . . . . . . . . 45 7.2.48 limiter 1 attack/release rate (0x2f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.49 limiter 1 attack/release threshold (0x30) . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2.50 limiter 2 attack/release rate (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2.51 limiter 2 attack/release threshold (0x32) . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2.52 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2.53 channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.2.54 channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.2.55 channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.2.56 channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2.57 channel i 2 s output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 51 7.2.58 channel i 2 s output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 51 7.2.59 channel i 2 s output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 51 7.2.60 channel i 2 s output mapping channels 7 and 8 (0x3a) . . . . . . . . . . . . . 52 7.2.61 coefficient address register 1 (0x3b) . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.2.62 coefficient address register 2 (0x3c) . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.2.63 coefficient b1 data register, bits 23:16 (0x3d) . . . . . . . . . . . . . . . . . . . . 52 7.2.64 coefficient b1 data register, bits 15:8 (0x3e) . . . . . . . . . . . . . . . . . . . . . 53 7.2.65 coefficient b1 data register, bits 7:0 (0x3f) . . . . . . . . . . . . . . . . . . . . . . 53 7.2.66 coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 53 7.2.67 coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 53 7.2.68 coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 53 7.2.69 coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 53 7.2.70 coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 53 7.2.71 coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 54 7.2.72 coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 54 7.2.73 coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 54 7.2.74 coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 54 7.2.75 coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 54 7.2.76 coefficient b0 data register, bits 15:8 (0x4a) . . . . . . . . . . . . . . . . . . . . . 54 7.2.77 coefficient b0 data register, bits 7:0 (0x4b) . . . . . . . . . . . . . . . . . . . . . . 54 7.2.78 coefficient write control register (0x4c) . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.3 reading a coefficient from ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.4 reading a set of coefficients from ram . . . . . . . . . . . . . . . . . . . . . . . . . . 55
STA309B contents doc id 022570 rev 2 5/66 7.5 writing a single coefficient to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.6 writing a set of coefficients to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8 equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.1 post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.2 variable maximum power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.2.1 mpcc1-2 (0x4d, 0x4e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.3 variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.3.1 dcc1-2 (0x4f, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.4 pscorrect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.4.1 psc1-2: ripple correction value (rcv) (0x51, 0x52) . . . . . . . . . . . . . . . 60 8.4.2 psc3: correction normalization value (cnv) (0x53) . . . . . . . . . . . . . . . 60 8.5 digital pop-free operation in single-ended mode . . . . . . . . . . . . . . . . . . . 60 8.5.1 pfcxon: digital pop-free register (0x5f) . . . . . . . . . . . . . . . . . . . . . . . 61 8.5.2 timing settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.5.3 ramptim: ramp duration register (0x66) . . . . . . . . . . . . . . . . . . . . . . . 62 8.5.4 tspupt: waiting time after eapd (0x67 - 0x68) . . . . . . . . . . . . . . . . . . 62 8.5.5 lspdwt: waiting time befo re eapd (0x71 - 0x72) . . . . . . . . . . . . . . . . 62 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
list of tables STA309B 6/66 doc id 022570 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. general interface electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 table 7. dc electrical characteristics: 3.3-v buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 table 8. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9. ram block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 10. vfqfpn-56 (8 x 8 mm) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 11. exposed pad variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
STA309B list of figures doc id 022570 rev 2 7/66 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. reference schematic for STA309B-based application . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 figure 8. channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 9. typical single-ended driver - power stage configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 10. pop-free timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 11. vfqfpn-56 (8 x 8 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
block diagram STA309B 8/66 doc id 022570 rev 2 1 block diagram figure 1. block diagram figure 2. channel signal flow out1a/b out2a/b out3a/b out4a/b out5a/b out6a/b out7a/b out8a/b lrcki bicki sdi12 sdi34 sdi56 sdi78 sa serial data in i 2 c channel mapping variable over- sampling treble, bass, eq (biquads ) volume limiting sdo78 sdo12 sdo34 sdo56 oversampling variable down- sampling power down pwdn eapd pll pllb xti ckout scl sda lrcko bicko mvo serial data out system control system timing ddx ffx 1x,2x,4x interp biquads b/ t volume limiter 2x interp distortion compensation ns c_con pwm ddx output interp_rate 8 inputs from i2s dsd conversion 6 inputs from dsd mapping/ mix #1 dsde mix #2 prescale high- pas s filter biq u ad #2 biquad #3 biquad #4 biq u ad #5 biquad #6 biquad #7 biq u ad #8 bas s hard set to -18db when automode eq (ameq) hard set coeecients when automode eq (ameq) hard set coeecients when au t omode bass management crossover (ambmxe) har d s et coeecients when deemphasis enabled (demp) from mix#1 engine or previous channel biq ua d # 1 0 output (cxblp) to mix#2 engine treble us er p r o ga m ma b le biquad #1 w hen high-pass bypassed (hpb) us er p rogrammable biquads #9 and #10 when tone bypassed (cxtcb)
STA309B pin connections doc id 022570 rev 2 9/66 2 pin connections figure 3. pin connections (top view) 1 mvo 2 gnd 3 vdd 4 gnd 5 sdi_78 6 sdi_56 7 sdi_34 8 sdi_12 9 lrcki 10 bicki 11 vdd 12 gnd 42 41 40 39 38 37 36 35 34 33 32 31 out2_a out2b gnd vdd out3_a out3_b out4_a out4_b out5_a out5_b gnd vdd 15 sa 16 sda 17 scl 18 xti 19 filter_pll 20 gnda 21 vdda 22 ckout 23 gnd 24 vdd 56 55 54 53 52 51 50 49 48 47 46 45 pwdn sdo_78 sdo_56 gnd vdd sdo_34 sdo_12 lrcko bicko gnd vdd eapd 13 reset 14 bypass 30 29 out6_a out6_b 44 43 out1_a out1_b 25 out8_b 26 out8_a 27 out7_b 28 out7_a vfqfpn-56
pin connections STA309B 10/66 doc id 022570 rev 2 table 2. pin description STA309B pin type name description 1 5-v tolerant ttl input buffer mvo/dsd_clk master volume override/ dsd input clock 5 5-v tolerant ttl input buffer sdi_78/dsd_6 input serial data channels 7 & 8/ dsd input channel 6 6 5-v tolerant ttl input buffer sdi_56/dsd_5 input serial data channels 5 & 6/ dsd input channel 5 7 5-v tolerant ttl input buffer sdi_34/dsd_4 input serial data channels 3 & 4/ dsd input channel 4 8 5-v tolerant ttl input buffer sdi_12/dsd_3 input serial data channels 1 & 2/ dsd input channel 3 9 5-v tolerant ttl input buffer lrcki/dsd_2 input left/right clock/ dsd input channel 2 10 5-v tolerant ttl input buffer bicki/dsd_1 input serial clock/ dsd input channel 1 13 5-v tolerant ttl schmitt trigger input buffer reset global reset 14 cmos input buffer with pull-down pll_bypass bypass phase locked loop 15 cmos input buffer with pull-down sa select address (i 2 c) 16 bidirectional buffer: 5-v tolerant ttl schmitt trigger input; 3.3-v capable 2 ma slew-rate controlled output sda serial data (i 2 c) 17 5-v tolerant ttl schmitt trigger input buffer scl serial clock (i 2 c) 18 5-v tolerant ttl schmitt trigger input buffer xti crystal oscillator input (clock input) 19 analog pad filter_pll pll filter 20 analog ground gnda pll ground 21 3.3v analog supply voltage vdda pll supply 22 3.3-v capable ttl tristate 4ma output buffer ckout clock output 25 3.3-v capable ttl 2ma output buffer out8b pwm channel 8 output b 26 3.3-v capable ttl 2ma output buffer out8a pwm channel 8 output a 27 3.3-v capable ttl 2ma output buffer out7b pwm channel 7 output b 28 3.3-v capable ttl 2ma output buffer out7a pwm channel 7 output a 29 3.3-v capable ttl 2ma output buffer out6b pwm channel 6 output b
STA309B pin connections doc id 022570 rev 2 11/66 30 3.3-v capable ttl 2ma output buffer out6a pwm channel 6 output a 33 3.3-v capable ttl 2ma output buffer out5b pwm channel 5 output b 34 3.3-v capable ttl 2ma output buffer out5a pwm channel 5 output a 35 3.3-v capable ttl 2ma output buffer out4b pwm channel 4 output b 36 3.3-v capable ttl 2ma output buffer out4a pwm channel 4 output a 37 3.3-v capable ttl 2ma output buffer out3b pwm channel 3 output b 38 3.3-v capable ttl 2ma output buffer out3a pwm channel 3 output a 41 3.3-v capable ttl 2ma output buffer out2b pwm channel 2 output b 42 3.3-v capable ttl 2ma output buffer out2a pwm channel 2 output a 43 3.3-v capable ttl 2ma output buffer out1b pwm channel 1 output b 44 3.3-v capable ttl 2ma output buffer out1a pwm channel 1 output a 45 3.3-v capable ttl 4ma output buffer eapd ext. amp power-down 48 3.3-v capable ttl 2ma output buffer bicko output serial clock 49 3.3-v capable ttl 2ma output buffer lrcko output left/right clock 50 3.3-v capable ttl 2ma output buffer sdo_12 output serial data channels 1&2 51 3.3-v capable ttl 2ma output buffer sdo_34 output serial data channels 3&4 54 3.3-v capable ttl 2ma output buffer sdo_56 output serial data channels 5&6 55 3.3-v capable ttl 2ma output buffer sdo_78 output serial data channels 7&8 56 5-v tolerant ttl schmitt trigger input buffer pwdn device power-down 3,11,21,24,31,39, 46,52 3.3-v digital supply voltage vdd 3.3-v supply 2,4,12,20,23,32, 40,47,53 digital ground gnd ground table 2. pin description (continued) STA309B pin type name description
electrical specifications STA309B 12/66 doc id 022570 rev 2 3 electrical specifications 3.1 absolute maximum ratings 3.2 thermal data 3.3 recommended operating conditions table 3. absolute maximum ratings symbol parameter min typ max unit v dd 3.3-v i/o power supply -0.5 4 v v dda 3.3-v logic power supply -0.5 4 v v i voltage on input pins -0.5 vdd + 0.5 v v o voltage on output pins -0.5 vdd + 0.3 v t stg storage temperature -40 150 c t amb ambient operating temperature -40 90 c table 4. thermal data symbol parameter min typ max unit r thj-case thermal resistance, junction-case (thermal pad) STA309B 1.5 c/w table 5. recommended operating conditions symbol parameter min typ max unit v dd i/o power supply 3.0 3.6 v v dda logic power supply 3.0 3.6 v t j operating junction temperature -40 125 c
STA309B electrical specifications doc id 022570 rev 2 13/66 3.4 electrical specifications the following specifications are valid for v dd = 3.3 v 0.3 v, v dda = 3.3 v 0.3 v and tamb = 0 to 70 c, unless otherwise stated. table 6. general interface electrical specifications symbol parameter conditions min typ max unit i il low-level input no pull-up v i = 0 v 1 (1) 1. the leakage currents are generally very small, < 1 na. the values given here are maximum after an electrostatic stress on the pin. a i ih high-level input no pull-down v i = v dd 2 a i oz tristate output leakage without pull-up/down v i = v dd 2 a v esd electrostatic protection (human body model) leakage < 1 a2000v table 7. dc electrical characteristics: 3.3-v buffers symbol parameter conditions min typ max unit v il low-level input voltage 0.8 v v ih high-level input voltage 2.0 v v ilhyst low-level threshold input falling 0.8 1.35 v v ihhyst high-level threshold input rising 1.3 2.0 v v hyst schmitt trigger hysteresis 0.3 0.8 v v ol low-level output ioi = 100 a 0.2 v v oh high-level output ioh = -100 a vdd- 0.2 v ioh = -2 ma 2.4 v
pin description STA309B 14/66 doc id 022570 rev 2 4 pin description master volume override (mvo) this pin enables the user to bypass the volu me control on all channels. when mvo is pulled high, the master volume register is set to 0x00, which corresponds to its full-scale setting. the master volume register setting offsets the individual channel volume settings, which default to 0 db. serial data in (sdi_12, sdi_34, sdi_56, sdi_78) audio information enters the device here. six format choices are available including i 2 s, left- or right-justified, lsb or msb first, with word widths of 16, 18, 20 and 24 bits. reset driving this pin low turns off the outputs and returns all settings to their defaults. i 2 c bus the sa, sda and scl pins operate per the phillips i 2 c specification. see section 5: i 2 c bus operation . phase locked loop (pll) the phase locked loop section provides the system timing signals and ckout. clock output (ckout) system synchronization and master clocks are provided by ckout. pwm outputs (out1 through out8) the pwm outputs provide the input signal for the power devices. external amplifier power-down (eapd) this signal can be used to control the power-down of ffx power devices. serial data out (sdo_12, sdo_34, sdo_56, sdo_78) these are the outputs for audio information. six different formats are available including i 2 s, left- or right-justified, lsb or msb first, with word widths of 16, 18, 20 and 24 bits. device power-down (pwdn) pulling pwdn low begins the power-down sequence which puts the STA309B into a low-power state. eapd (pin 51) goes low approximately 30 ms later.
STA309B i 2 c bus operation doc id 022570 rev 2 15/66 5 i 2 c bus operation the STA309B supports the i 2 c protocol via the input ports scl and sda_in (master to slave) and the output port sda_out (slave to master). this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the STA309B is always a slave device in all of its communications. 5.1 communication protocol 5.1.1 data transition or change data changes on the sda line must only occur when the scl clock is low. an sda transition while the clock is high is used to identify a start or stop condition. 5.1.2 start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 5.1.3 stop condition stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between the STA309B and the bus master. 5.1.4 data input during the data input the STA309B samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 5.2 device addressing to start communication between the master and the omega ffx core, the master must initiate with a start condition. following this , the master sends 8 bits to the sda line (msb first) corresponding to the device select address and read or write mode. the 7 most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the STA309B the i 2 c interface has two device addresses depending on the sa port configuration, 0x40 or 0100000x when sa = 0, and 0x42 or 0100001x when sa = 1. the 8 th bit (lsb) identifies read or write operation rw, this bit is set to 1 in read mode and 0 for write mode. after a start condition, the STA309B identifies on the bus the device address and if a match is found, it acknowledges the identification on the sda bus during
i 2 c bus operation STA309B 16/66 doc id 022570 rev 2 the 9 th -bit time. the byte following the device identification byte is the internal space address. 5.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the STA309B acknowledges this and then waits for the byte of internal address. after receiving the internal byte address the STA309B again responds with an acknowledgement. 5.3.1 byte write in the byte write mode the master sends one data byte, this is acknowledged by the ffx core. the master then terminates the transfer by generating a stop condition. 5.3.2 multi-byte write the multi-byte write modes can start from any internal address. the master generating a stop condition terminates the transfer. figure 4. write mode sequence figure 5. read mode sequence dev-addr ack start rw sub-addr ack data in a ck stop byte write dev-addr ack start rw sub-addr ack data in a ck stop multibyte write data in a ck dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr a ck stop random address read data no a ck w r t r a t s dev-addr ack start data ack data ack stop sequential current read data no a ck dev-addr ack start rw sub-addr ack dev-addr a ck sequential random read data a ck w r t r a t s data a ck no a ck stop data rw= high
STA309B application reference schematic doc id 022570 rev 2 17/66 6 application reference schematic figure 6. reference schematic for STA309B-based application gnda vdda ch5_a ch5_b scl sdata2 bick mclk power_on_rst eapd sdata1 sdata0 sda lrck pwrdwn ch1_a ch1_b ch2_b ch2_a ch6_b ch3_b ch3_a ch4_a ch4_b ch6_a +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v c23 100nf y5v eia0603 c23 100nf y5v eia0603 c12 100nf y5v eia0603 c12 100nf y5v eia0603 c6 100nf y5v eia0603 c6 100nf y5v eia0603 1 2 l1 600 ohm@100mhz eia0805 l1 600 ohm@100mhz eia0805 c14 100nf y5v eia0603 c14 100nf y5v eia0603 c16 100pf npo eia0603 c16 100pf npo eia0603 r6 0 0000-0603 r6 0 0000-0603 c157 47pf npo eia0603 c157 47pf npo eia0603 c5 100nf y5v eia0603 c5 100nf y5v eia0603 1 2 l3 600 ohm@100mhz eia0805 l3 600 ohm@100mhz eia0805 r15 3.40k 0603 r15 3.40k 0603 c19 220pf npo eia0603 c19 220pf npo eia0603 + c22 22uf 6.3vdc eia3528_b + c22 22uf 6.3vdc eia3528_b c18 100nf y5v eia0603 c18 100nf y5v eia0603 vdd3.3_1 3 sdi_12 9 sdi_34 8 gnd_2 13 reset 15 sdi_56 7 sda 18 scl 19 sa 17 mvo 1 vdd3.3_3 28 xti 20 gnd_3 27 vdda_pll 22 pll_bypass 16 pll_filter 21 gnda_pll 23 gnd_5 45 nc 46 46 out2_b 47 out2_a 48 out1_b 49 out1_a 50 gnd_7 60 nc 61 61 eapd 51 lrcko 56 sdo_12 57 sdo_34 58 sdo_56 62 bicko 55 gnd_6 53 vdd3.3_6 52 ckout 25 pwdn 64 sdi_78 6 bicki 11 lrcki 10 vdd3.3_2 12 nc 14 14 nc 26 26 nc 37 37 nc 54 54 sdo_78 63 vdd3.3_7 59 out3_a 43 out3_b 42 out4_a 41 out4_b 40 out5_a 39 out5_b 38 out6_a 34 out6_b 33 out7_a 32 out7_b 31 out8_a 30 out8_b 29 vdd3.3_5 44 test_mode 2 gnd_1 4 nc 5 5 vdd3.3_4 35 gnd_4 36 vdd3.3_pll 24 u2 sta308a u2 sta308a + c4 2.2uf 6.3vdc eia3216_a + c4 2.2uf 6.3vdc eia3216_a r14 0 0000-0603 r14 0 0000-0603 c20 100nf y5v eia0603 c20 100nf y5v eia0603 c147 1000pf npo eia0805 c147 1000pf npo eia0805 c155 1000pf npo eia0603 c155 1000pf npo eia0603 c15 1200pf x7r eia0603 c15 1200pf x7r eia0603 c145 100nf y5v eia0603 c145 100nf y5v eia0603 c25 100nf y5v eia0603 c25 100nf y5v eia0603 c24 100nf y5v eia0603 c24 100nf y5v eia0603 the pll filter m us t b e pl a ced as clo s e as po ss i b le to the s ta 3 09b pin s
registers STA309B 18/66 doc id 022570 rev 2 7 registers 7.1 register summary table 8. register summary addr name d7 d6 d5 d4 d3 d2 d1 d0 configuration 0x00 confa cos1 cos0 dspb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb saifb sai3 sai2 sai1 sai0 0x02 confc saofb sao3 sao2 sao1 sao0 0x03 confd mpc csz4 csz3 csz2 csz1 csz0 om1 om0 0x04 confe c8bo c7bo c6bo c5bo c4bo c3bo c2bo c1bo 0x05 conff pwms2 pwms1 pwms0 bql psl demp drc hpb 0x06 confg mpcv dccv hpe am2e ame cod sid pwmd 0x07 confh ecle ldte bcle ide zde sve zce nsbw 0x08 confi eapd psce volume control 0x09 mmute mmute 0x0a mvol mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 0x0b c1vol c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0x0c c2vol c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0x0d c3vol c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 0x0e c4vol c4v7 c4v6 c4v5 c4v4 c4v3 c4v2 c4v1 c4v0 0x0f c5vol c5v7 c5v6 c5v5 c5v4 c5v3 c5v2 c5v1 c5v0 0x10 c6vol c6v7 c6v6 c6v5 c6v4 c6v3 c6v2 c6v1 c6v0 0x11 c7vol c7v7 c7v6 c7v5 c7v4 c7v3 c7v2 c7v1 c7v0 0x12 c8vol c8v7 c8v6 c8v5 c8v4 c8v3 c8v2 c8v1 c8v0 0x13 c1vtmb c1m c1vbp c1vt4 c1vt3 c1vt2 c1vt1 c1vt0 0x14 c2vtmb c2m c2vbp c2vt4 c2vt3 c2vt2 c2vt1 c2vt0 0x15 c3vtmb c3m c3vbp c3vt4 c3vt3 c3vt2 c3vt1 c3vt0 0x16 c4vtmb c4m c4vbp c4vt4 c4vt3 c4vt2 c4vt1 c4vt0 0x17 c5vtmb c5m c5vbp c5vt4 c5vt3 c5vt2 c5vt1 c5vt0 0x18 c6vtmb c6m c6vbp c6vt4 c6vt3 c6vt2 c6vt1 c6vt0 0x19 c7vtmb c7m c7vbp c7vt4 c7vt3 c7vt2 c7vt1 c7vt0 0x1a c8vtmb c8m c8vbp c8vt4 c8vt3 c8vt2 c8vt1 c8vt0
STA309B registers doc id 022570 rev 2 19/66 input mapping 0x1b c12im c2im2 c2im1 c2im0 c1im2 c1im1 c1im0 0x1c c34im c4im2 c4im1 c4im0 c3im2 c3im1 c3im0 0x1d c56im c6im2 c6im1 c6im0 c5im2 c5im1 c5im0 0x1e c78im c8im2 c8im1 c8im0 c7im2 c7im1 c7im0 automode 0x1f auto1 amdm amgc2 amgc1 amgc0 amv1 amv0 ameq1 ameq0 0x20 auto2 sub rss1 rss0 css1 css0 fss ambmxe ambmme 0x21 auto3 amam2 amam1 amam0 amame msa amps 0x22 preeq xo2 xo1 xo0 peq4 peq3 peq2 peq1 peq0 0x23 ageq ageq4 ageq3 ageq2 ageq1 ageq0 0x24 bgeq bgeq4 bgeq3 bgeq2 bgeq1 bgeq0 0x25 cgeq cgeq4 cgeq3 cgeq2 cgeq1 cgeq0 0x26 dgeq dgeq4 dgeq3 dgeq2 dgeq1 dgeq0 0x27 egeq egeq4 egeq3 egeq2 egeq1 egeq0 processing loop 0x28 bqlp c8blp c7blp c6blp c5blp c4blp c3blp c2blp c1blp 0x29 mxlp c8mxlp c7mxlp c6mxlp c5mxlp c4mxlp c3mxlp c2mxlp c1mxlp processing bypass 0x2a eqbp c8eqbp c7eqbp c6eqbp c5eqbp c4eqbp c3eqbp c2eqbp c1eqbp 0x2b tonebp c8tcb c7tcb c6tcb c5tcb c4tcb c3tcb c2tcb c1tcb tone control 0x2c tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 dynamics control 0x2d c1234ls c4ls1 c4ls0 c3ls1 c3ls0 c2ls1 c2ls0 c1ls1 c1ls0 0x2e c5678ls c8ls1 c8ls0 c7ls1 c7ls0 c6ls1 c6ls0 c5ls1 c5ls0 0x2f l1ar l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0x30 l1atrt l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0x31 l2ar l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0x32 l2atrt l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 pwm output timing 0x33 c12ot c2ot2 c2ot1 c2ot0 c1ot2 c1ot1 c1ot0 0x34 c34ot c4ot2 c4ot1 c4ot0 c3ot2 c3ot1 c3ot0 table 8. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0
registers STA309B 20/66 doc id 022570 rev 2 0x35 c56ot c6ot2 c6ot1 c6ot0 c5ot2 c5ot1 c5ot0 0x36 c78ot c8ot2 c8ot1 c8ot0 c7ot2 c7ot1 c7ot0 i 2 s output channel mapping 0x37 c12om c2om2 c2om1 c2om0 c1om2 c1om1 c1om0 0x38 c34om c4om2 c4om1 c4om0 c3om2 c3om1 c3om0 0x39 c56om c6om2 c6om1 c6om0 c5om2 c5om1 c5om0 0x3a c78om c8om2 c8om1 c8om0 c7om2 c7om1 c7om0 user-defined coefficient ram 0x3b cfaddr1 cfa9 cfa8 0x3c cfaddr2 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0x3d b1cf1 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0x3e b1cf2 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0x3f b1cf3 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 0x40 b2cf1 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 0x41 b2cf2 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 0x42 b2cf3 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 0x43 a1cf1 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16 0x44 a1cf2 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 0x45 a1cf3 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 0x46 a2cf1 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 0x47 a2cf2 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 0x48 a2cf3 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 0x49 b0cf1 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 0x4a b0cf2 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 0x4b b0cf3 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 0x4c cfud wa w1 0x4d mpcc1 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0x4e mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x4f dcc1 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 0x50 dcc2 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 0x51 psc1 rcv11 rcv10 rcv9 rcv8 rcv7 rcv6 rcv5 rcv4 0x52 psc2 rcv3 rcv2 rcv1 rcv0 cnv11 cnv10 cnv9 cnv8 0x53 psc3 cnv7 cnv6 cnv5 cnv4 cnv3 cnv2 cnv1 cnv0 table 8. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0
STA309B registers doc id 022570 rev 2 21/66 digital pop-free 0x57 pfcxon ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 0x60reserved-------- 0x61reserved-------- 0x62reserved-------- 0x63reserved-------- 0x64reserved-------- 0x65reserved-------- 0x66 ramptim tr7 tr6 tr5 tr4 tr3 tr2 tr1 tr0 0x67 tspupt1 tp15 tp14 tp13 tp12 tp11 tp10 tp9 tp8 0x68 tspupt0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 0x69reserved-------- 0x6areserved-------- 0x6breserved-------- 0x6creserved-------- 0x70reserved-------- 0x71 lspdwt1 tl15 tl14 t l13 tl12 tl11 tl10 tl9 tl8 0x72 lspdwt0 tl7 tl6 tl5 tl4 tl3 tl2 tl1 tl table 8. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0
registers STA309B 22/66 doc id 022570 rev 2 7.2 register description 7.2.1 configuration register a (0x00) the STA309B supports sampling rates of 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, 192 khz, and 2.8224 mhz dsd. therefore the internal clocks are: 65.536 mhz for 32 khz 90.3168 mhz for 44.1 khz, 88.2 khz, 176.4 khz, and dsd 98.304 mhz for 48 khz, 96 khz, and 192 khz the external clock frequency provided to the xti pin must be a multiple of the input sampling frequency (fs). the relationship between the input clock and the input sampling rate is determined by both the mcsn and the irn (input rate) register bits. the mcsn bits determine the pll factor generating the internal clock and the irn bits determine the oversampling ratio used internally. interpolation ratio select the STA309B has variable interpolation (oversampling) settings such that internal processing and ffx output rates remain consis tent. the first processing block interpolates by either 4 times, 2 times, or 1 time (pass-through). the oversampling ratio of this interpolation is determined by the ir bits. d7 d6 d5 d4 d3 d2 d1 d0 cos1 cos0 dspb ir1 ir0 mcs2 mcs1 mcs0 10000011 bit rw rst name description 0rw1 mcs0 master clock select: sele cts the ratio between the input i 2 s sampling frequency and the input clock 1rw1 mcs1 2rw0 mcs2 input sampling rate fs (khz) ir mcs[2:0] 1xx 011 010 001 000 32, 44.1, 48 00 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs 88.2, 96 01 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs 176.4, 192 10 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs dsd 11 2 * fs 4 * fs 6 * fs 8 * fs 10 * fs bit rw rst name description 3 rw 0 ir0 interpolation ratio select: selects internal interpolation ratio based on input i 2 s sampling frequency 4rw 0 ir1
STA309B registers doc id 022570 rev 2 23/66 i setting the dspb bit bypasses the bi quad function of the ffx core. ir[1,0] input sampling rate fs (khz) 1 st stage interpolation ratio 00 32 4-times oversampling 00 44.1 4-times oversampling 00 48 4-times oversampling 01 88.2 2-times oversampling 01 96 2-times oversampling 10 176.4 pass-through 10 192 pass-through 11 dsd dsd to 176.4 khz conversion bit rw rst name description 0 rw 0 dspb dsp bypass bit: 0: normal operation 1: bypass of biquad and bass/treble functions cos[1,0] ckout frequency 00 pll output 01 pll output / 4 10 pll output / 8 11 pll output / 16
registers STA309B 24/66 doc id 022570 rev 2 7.2.2 configuration register b (0x01) - serial input formats serial data interface the STA309B audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. the STA309B always acts a slave when receiving audio input from standard digital audio components. serial data for eight channels is provided using 6 input pins: left/right clock lrcki (pin 10), serial clock bicki (pin 11), serial data 1 and 2 sdi12 (pin 9), serial data 3 and 4 sdi34 (pin 8), serial data 5 and 6 sdi56 (pin 7), and serial data 7 and 8 sdi78 (pin 6). the sai/saifb register (configuration register b, address 0x01) is used to specify the serial data format. the default serial data format is i 2 s, msb-first. available formats are shown in the tables that follow. note: serial input and output formats are specified separately for example, sai = 1110 and saifb = 1 specifies right-justified 16-bit data, lsb-first. d7 d6 d5 d4 d3 d2 d1 d0 saifb sai3 sai2 sai1 sai0 00000 bit rw rst name description 0 rw 0 sai0 serial audio input interface format: determines the interface format of the input serial digital audio interface. 1 rw 0 sai1 2 rw 0 sai2 3 rw 0 sai3 bit rw rst name description 4 rw 0 saifb determines msb or lsb first for all sao formats: 0: msb first 1: lsb first
STA309B registers doc id 022570 rev 2 25/66 the table below lists the serial audio input formats supported by the STA309B as related to bicki = 32 * fs, 48 * fs, 64 * fs , where sampling rate, fs = 32, 44.1, 48, 88.2, 96, 176.4, 192 khz. bicki sai [3:0] saifb interface format 32 * fs 1100 x i 2 s 15-bit data 1110 x left/right-justified 16-bit data 48 * fs 0100 x i 2 s 23-bit data 0100 x i 2 s 20-bit data 1000 x i 2 s 18-bit data 0100 0 msb-first i 2 s 16-bit data 1100 1 lsb-first i 2 s 16-bit data 0001 x left-justified 24-bit data 0101 x left-justified 20-bit data 1001 x left-justified 18-bit data 1101 x left-justified 16-bit data 0010 x right-justified 24-bit data 0110 x right-justified 20-bit data 1010 x right-justified 18-bit data 1110 x right-justified 16-bit data 64 * fs 0000 x i 2 s 24-bit data 0100 x i 2 s 20-bit data 1000 x i 2 s 18-bit data 0000 0 msb-first i 2 s 16-bit data 1100 1 lsb-first i 2 s 16-bit data 0001 x left-justified 24-bit data 0101 x left-justified 20-bit data 1001 x left-justified 18-bit data 1101 x left-justified 16-bit data 0010 x right-justified 24-bit data 0110 x right-justified 20-bit data 1010 x right-justified 18-bit data 1110 x right-justified 16-bit data
registers STA309B 26/66 doc id 022570 rev 2 7.2.3 configuration register c (0x02) - serial output formats the STA309B features a serial audio output interface that consists of 8 channels. the serial audio output always acts as a slave to the serial audio input interface and, therefore, all output clocks are synchronous with the input clocks. the output sampling frequency (fs) is also equivalent to the input sampling frequency. in the case of sacd/dsd and pdm input, the serial audio output acts as a master with an output sampling frequency of 176.4 khz. the output serial format can be selected independently from the input format and is done via the sao and saofb bits. d7 d6 d5 d4 d3 d2 d1 d0 saofb sao3 sao2 saio sao0 00000 bit rw rst name description 0rw 0 sao0 serial audio output interface format: determines the interface format of the output serial digital audio interface. 1rw 0 sao1 2rw 0 sao2 3rw 0 sao3 bit rw rst name description 4rw 0 saofb determines msb or lsb first for all sao formats: 0: msb first 1: lsb first bicki = bicko sao[3:0] interface data format 32 * fs 0111 i 2 s data 1111 left/right-justified 16-bit data 48 * fs 1110 i 2 s data 0001 left-justified data 1010 right-justified 24-bit data 1011 right-justified 20-bit data 1100 right-justified 18-bit data 1101 right-justified 16-bit data 64 * fs 0000 i 2 s data 0001 left-justified data 0010 right-justified 24-bit data 0011 right-justified 20-bit data 0100 right-justified 18-bit data 0101 right-justified 16-bit data
STA309B registers doc id 022570 rev 2 27/66 7.2.4 configuration register d (0x03) the ffx power output mode selects how the ffx output timing is configured. different power devices use different output modes. the sta50x recommended use is om = 10. setting the mpc bit turns on special processing that corrects the sta50x power device at high power. this mode should lower the thd+n of a full sta50x ffx system at maximum power output and slightly below. this mode will only be operational at om[1,0] = 01. d7 d6 d5 d4 d3 d2 d1 d0 mpc csz4 csz3 csz2 csz1 csz0 om1 om0 11000010 bit rw rst name description 0rw 0 om0 ffx power output mode: se lects configuration of ffx output 1rw 1 om1 om[1,0] output stage - mode 00 sta50x/sta51xb - drop compensation 01 discrete output stage - tapered compensation 10 sta50x/sta51xb - full power mode 11 variable drop compensation (cszn bits) bit rw rst name description 2rw 0 csz0 contra size register: when om[1,0] = 11, this register determines the size of the ffx compensating pulse from 0 clock ticks to 31 clock periods. 3rw 0 csz1 4rw 0 csz2 5rw 0 csz3 6rw 1 csz4 csz[4:0] compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size ?? 11111 31 clock period compensating pulse size bit rw rst name description 7rw 1 mpc max power correction: setting to 1 enables sta50x correction for thd reduction near maximum power output
registers STA309B 28/66 doc id 022570 rev 2 7.2.5 configuration register e (0x04) each individual channel output can be set to output a binary pwm stream. in this mode output a of a channel will be considered the positive output and output b is the negative inverse. 7.2.6 configurati on register f (0x05) the STA309B features an internal digital high-pass filter for the purpose of ac coupling. the purpose of this filter is to prevent dc signals from passing through an ffx amplifier. dc signals can cause speaker damage. if hpb = 1, then the filter that the high-pass filter utilizes is made available as user- programmable biquad #1. both limiters can be used in one of two ways, anti-clipping or dynamic range compression. when used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. d7 d6 d5 d4 d3 d2 d1 d0 c8bo c7bo c6bo c5bo c4bo c3bo c2bo c1bo 00000000 bit rw rst name description 0rw 0 c1bo channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output mode enable bits. a setting of 0 indicates ordinary ffx tristate output. a setting of 1 indicates binary output mode 1rw 0 c2bo 2rw 0 c3bo 3rw 0 c4bo 4rw 0 c5bo 5rw 0 c6bo 6rw 0 c7bo 7rw 0 c8bo d7 d6 d5 d4 d3 d2 d1 d0 pwms2 pwms1 pwms0 bql psl demp drc hpb 00000000 bit rw rst name description 0rw 0 hpb high-pass filter bypass bit: setting to one bypasses the internal ac coupling digital high-pass filter bit rw rst name description 1 rw 0 drc dynamic range compression/anti-clipping 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode
STA309B registers doc id 022570 rev 2 29/66 in dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of th e volume level. by setting this bit to one, de-emphasis will be implemented on all channels. when this is used, it takes the place of biquad #7 in each channel and any coefficients using biquad #1 will be ignored. the dspb (d sp bypass) bit must be set to 0 for de-emphasis to function. post-scale functionality can be used for power-supply error correction. for multichannel applications running off the same power supply, the post-scale values can be linked to the value of channel 1 for ease of use and in order to update the values faster. for ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. bit rw rst name description 2rw 0 demp de-emphasis: 0: no de-emphasis 1: de-emphasis bit rw rst name description 3 rw 0 psl post-scale link: 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value bit rw rst name description 4rw 0 bql biquad link: 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values bit rw rst name description 7:5 rw 00 pwms[2:0] pwm speed selection: pwms[1:0] pwm output speed 000 normal speed (384 khz) (all channels) 001 half-speed (192 khz) (all channels) 010 double-speed (768 khz) (all channels) 011 normal speed (channels 1-6), double-speed (channels 7-8) 100 odd speed (341.3 khz) (all channels)
registers STA309B 30/66 doc id 022570 rev 2 7.2.7 configuration register g (0x06) the STA309B features an ffx processing mode that minimizes the amount of noise generated in the frequency range of am radio. this mode is intended for use when ffx is operating in a device with an active am tuner. the snr of the ffx processing is reduced to ~83 db in this mode, which is still gr eater than the snr of am radio. the STA309B features 2 ffx processing modes that minimize the amount of noise generated in the frequency range of am radio. this second mode is intended for use when ffx is operating in a device with an active am tuner. this mode eliminates the noise- shaper. channels 7 and 8 can be configured to be processed and output in such a manner that headphones can be driven using an appropriate output device. this signal is a differential 3-wire drive called ffx headphone. d7 d6 d5 d4 d3 d2 d1 d0 mpcv dccv hpe am2e ame cod sid pwmd 00000000 bit rw rst name description 0rw0 pwmd pwm output disable: 0: pwm output normal 1: no pwm output 1rw0 sid serial interface (i 2 s out) disable: 0: i 2 s output normal 1: no i 2 s output 2rw0 cod clock output disable: 0: clock output normal 1: no clock output bit rw rst name description 3rw 0 ame am mode enable: 0: normal ffx operation. 1: am reduction mode ffx operation bit rw rst name description 4rw 0 am2e am2 mode enable: 0: normal ffx operation 1: am2 reduction mode ffx operation bit rw rst name description 5rw 0 hpe ffx headphone enable: 0: channels 7 and 8 normal ffx operation 1: channels 7 and 8 headphone operation
STA309B registers doc id 022570 rev 2 31/66 7.2.8 configuration register h (0x07) the zce bit enables zero-crossing volume adju stments. when the volu me is adjusted on digital zero-crossings, no clicks will be audible. setting the zde bit enables the zero-detect automatic mute. the zero-detect circuit looks at the input data of each processing channel afte r the channel-mapping block. if any channel receives 2048 consecutive zero-value samples (regardless of fs), then that individual channel is muted if this function is enabled. bit rw rst name description 6 rw 0 dccv distortion compensation variable enable : 0: uses preset dc coefficient 1: uses dcc coefficient bit rw rst name description 7rw 0 mpcv max power correction variable: 0: uses standard mpc coefficient 1: uses mpcc bits for mpc coefficient d7 d6 d5 d4 d3 d2 d1 d0 ecle ldte bcle ide zde sve zce nsbw 01111110 bit rw rst name description 0 rw 0 nsbw noise-shaper bandwidth selection: 1: 3 rd order ns 0: 4 th order ns bit rw rst name description 1rw1 zce zero-crossing volume enable: 1: volume adjustments will only occur at digital zero- crossings 0: volume adjustments will occur immediately bit rw rst name description 2rw1 sve soft volume enable: 1: volume adjustments use soft volume 0: volume adjustments occur immediately bit rw rst name description 3rw1 zde zero-detect mute enable: setting to 1 enables the automatic zero-detect mute
registers STA309B 32/66 doc id 022570 rev 2 setting the ide bit enables this function, which looks at the input i 2 s data and will automatically mute if the signals are perceived as invalid. this function detects loss of input mclk in binary mode and will output 50% duty cycle. this function actively prevents double triggering of lrclk. device power-down signal (eapd) on clock loss detection. this function is enabled by default. it is strongly recommended to avoid spurious noise during the on-off sequence. the STA309B has the ecle bit set to 0. 7.2.9 configuration register i (0x08) this feature utilizes an adc on sdi78 that pr ovides power supply ripple information for correction. regist ers psc1, psc2, psc3 are utilized in this mode. bit rw rst name description 4rw 1 ide invalid input detect mute enable: 1: enables the automatic invalid input detect mute bit rw rst name description 5 rw 1 bcle binary output mode clock loss detection enable bit rw rst name description 6 rw 1 ldte lrclk double triggering protection enable bit rw rst name description 7 rw 1 ecle auto eapd on clock loss d7 d6 d5 d4 d3 d2 d1 d0 eapd psce 0 0 bit rw rst name description 0 rw 0 psce power supply ripple correction enable: 0: normal operation 1: pscorrect operation bit rw rst name description 7 rw 0 eapd external amplifier power-down: 0: external power-stage power-down active 1: normal operation
STA309B registers doc id 022570 rev 2 33/66 7.2.10 master mute register (0x09) 7.2.11 master volu me register (0x0a) note: the value of the volume derived from mvol is dependent on the amv automode volume settings. 7.2.12 channel 1 volume (0x0b) 7.2.13 channel 2 volume (0x0c) 7.2.14 channel 3 volume (0x0d) 7.2.15 channel 4 volume (0x0e) d7 d6 d5 d4 d3 d2 d1 d0 mmute 0 d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 11111111 d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c4v7 c4v6 c4v5 c4v4 c4v3 c4v2 c4v1 c4v0 01100000
registers STA309B 34/66 doc id 022570 rev 2 7.2.16 channel 5 volume (0x0f) 7.2.17 channel 6 volume (0x10) 7.2.18 channel 7 volume (0x11) 7.2.19 channel 8 volume (0x12) 7.2.20 channel 1 volume trim, mute, bypass (0x13) 7.2.21 channel 2 volume trim, mute, bypass (0x14) 7.2.22 channel 3 volume trim, mute, bypass (0x15) d7 d6 d5 d4 d3 d2 d1 d0 c5v7 c5v6 c5v5 c5v4 c5v3 c5v2 c5v1 c5v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c6v7 c6v6 c6v5 c6v4 c6v3 c6v2 c6v1 c6v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c7v7 c7v6 c7v5 c7v4 c7v3 c7v2 c7v1 c7v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c8v7 c8v6 c8v5 c8v4 c8v3 c8v2 c8v1 c8v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c1m c1vbp c1vt4 c1vt3 c1vt2 c1vt1 c1vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c2m c2vbp c2vt4 c2vt3 c2vt2 c2vt1 c2vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c3m c3vbp c3vt4 c3vt3 c3vt2 c3vt1 c3vt0 00010000
STA309B registers doc id 022570 rev 2 35/66 7.2.23 channel 4 volume trim, mute, bypass (0x16) 7.2.24 channel 5 volume trim, mute, bypass (0x17) 7.2.25 channel 6 volume trim, mute, bypass (0x18) 7.2.26 channel 7 volume trim, mute, bypass (0x19) 7.2.27 channel 8 volume trim, mute, bypass (0x1a) the volume structure of the STA309B consists of individual volume registers for each channel and a master volume register that provides an offset to each channel?s volume setting. there is also an additional offset for each channel called the channel volume trim. the individual channel volumes are adjustable in 0.5 db steps from +48 db to -78 db. as an example if c5v = 0xxx or +xxx db and mv = 0xxx or -xx db, then the total gain for channel 5 = xx db. the channel volume trim is adjustable independently on each channel from -10 db to +10 db in 1 db steps. the master mute when set to 1 will mute all channels at once, whereas the individual channel mutes (c nm) will mute only that channel. both the master mute and the channel mutes provide a "soft mute" with the volume ramping down to mute in 8192 samples from the maximum volume setting at the internal processing rate (~192 khz). a "hard mute" can be obtained by commanding a value of 0xff (255) to any channel volume register or the master volume register. when volume offsets are provided via the master volume register, any channel wh ose total volume is le ss than -91 db will be muted. all changes in volume take place at zero-crossings when zce = 1 (configuration register h) on a per-channel basis as th is creates the smoothest possible volume d7 d6 d5 d4 d3 d2 d1 d0 c4m c4vbp c4vt4 c4vt3 c4vt2 c4vt1 c4vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c5m c5vbp c5vt4 c5vt3 c5vt2 c5vt1 c5vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c6m c6vbp c6vt4 c6vt3 c6vt2 c6vt1 c6vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c7m c7vbp c7vt4 c7vt3 c7vt2 c7vt1 c7vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c8m c8vbp c8vt4 c8vt3 c8vt2 c8vt1 c8vt0 00010000
registers STA309B 36/66 doc id 022570 rev 2 transitions. when zce = 0, volume updates occur immediately. each channel also contains an individual channel volume bypass. if a pa rticular channel has volume bypassed via the cnvbp = 1 register, then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. each channel also contains a channel mute. if cnm = 1, a soft mute is performed on that channel. mv[7:0] volume offset from channel value 0x00 0 db 0x01 -0.5 db 0x02 -1 db ?? 0x4c -38 db ?? 0xfe -127 db 0xff hardware channel mute cnv[7:0] volume 0x00 +48 db 0x01 +47.5 db 0x02 +47 db ?? 0x5f +0.5 db 0x60 0 db 0x61 -0.5 db ?? 0xfe -79.5 db 0xff hardware channel mute cnvt[4:0] volume 0x00 to 0x06 +10 db 0x07 +9 db ?? 0x0f +1 db 0x10 0 db 0x11 -1 db ?? 0x19 -9 db 0x1a to 0x1f -10 db
STA309B registers doc id 022570 rev 2 37/66 7.2.28 channel input m apping channels 1 and 2 (0x1b) 7.2.29 channel input m apping channels 3 and 4 (0x1c) 7.2.30 channel input m apping channels 5 and 6 (0x1d) 7.2.31 channel input m apping channels 7 and 8 (0x1e) each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping re gisters. this allows for flexibilit y in processing, simplifies output stage designs, and enab les the ability to perform crossovers . the default settings of these registers map each i 2 s input channel to its corresponding processing channel. d7 d6 d5 d4 d3 d2 d1 d0 c2im2 c2im1 c2im0 c1im2 c1im1 c1im0 001 000 d7 d6 d5 d4 d3 d2 d1 d0 c4im2 c4im1 c4im0 c3im2 c3im1 c3im0 011 010 d7 d6 d5 d4 d3 d2 d1 d0 c6im2 c6im1 c6im0 c5im2 c5im1 c5im0 101 100 d7 d6 d5 d4 d3 d2 d1 d0 c8im2 c8m1 c8im0 c7im2 c7im1 c7im0 111 110 cnim[2:0] seria l input from 000 channel 1 001 channel 2 010 channel 3 011 channel 4 100 channel 5 101 channel 6 110 channel 7 111 channel 8
registers STA309B 38/66 doc id 022570 rev 2 7.2.32 auto1 - autom odes eq, volume, gc (0x1f) by setting ameq to any setting other than 00 enables automode eq, biquads 1-5 are not user programmable. any coefficient settings for these biquads will be ignored. also when automode eq is used, the pre-scale value for channels 1-6 becomes hard-set to -18 db. the automode downmix setting uses channels 7-8 of mix#1 engine and therefore these channels of this function are fixed and not allowed to be set by the user when in this mode. channels 1-6 must be arranged via channel mapping (registers cnim), if necessary, in the following manner for this operation: channel 1: left channel 2: right channel 3: left surround channel 4: right surround channel 5: center channel 6: lfe d7 d6 d5 d4 d3 d2 d1 d0 amdm amgc2 amgc1 amgc0 amv1 amv0 ameq1 ameq0 00000000 bit rw rst name description 1:0 rw 0 ameq[1:0] biquad 2-6 mode is: 00: user-programmable 01: preset eq - peq bits 10: graphic eq - xgeq bits 11: auto volume controlled loudness curve bit rw rst name description 3:2 rw 0 amv[1:0] automode volume mode (mvol) is: 00: mvol 0.5 db 256 steps (standard) 01: mvol auto curve 30 steps 10: mvol auto curve 40 steps 11: mvol auto curve 50 steps 6:4 rw 0 amgc[2:0] automode gain compression/limiters mode is: 000: user programmable gc 001: ac no clipping 010: ac limited clipping (10%) 011: drc nighttime listening mode 100: drc tv commercial/channel agc 101: ac 5.1 no clipping 110: ac 5.1 limited clipping (10%) bit rw rst name description 7rw 0 amdm automode 5.1 downmix: 0: normal operation 1: channels 7-8 are 2-channel downmix of channels 1-6
STA309B registers doc id 022570 rev 2 39/66 7.2.33 auto2 - automodes bass management2 (0x20) setting the ambmme bit enables the proper mixing to take place for various preset bass management configurations. setting the ambmxe bit enables the proper crossover filtering in biquad #7 to take place. the crossover for bass management is always 2 nd order (24 db/oct) and the crossover frequency is determined by register bits preeq.xo[2:0]. all configurations of dolby bass management can be performed in the ic. these different configurations are selected as they would be by the end-user. the automode bass management settin gs utilize channels 1-6 in the mix #1 engine, channels 1-6 biquad #6, and channels 1-2 in the mix #2 engine in configuration #2. these functions cannot be user-programmed while the bass management automode is active. not all settings are valid as some configurations are unlikely and do not have to be supported by dolby specifications. automatic crossover settings are provided or custom crossovers can be implemented using the available programmable biquads. input channels must be mapped using the channel-mapping feature in the following manner for bass management to be performed properly. 1: left front 2: right front 3: left rear 4: right rear 5: center 6: lfe d7 d6 d5 d4 d3 d2 d1 d0 sub rss1 rss0 css1 css0 fss ambmxe ambmme 10000000 bit rw rst name description 0 rw 0 ambmme 0: automode bass management mix disabled 1: automode bass management mix enabled bit rw rst name description 1 rw 0 ambmxe 0: automode bass management crossover disabled 1: automode bass management crossover enabled bitfield 10 01 00 css - center speaker size off large small rss - rear speaker size off large small
registers STA309B 40/66 doc id 022570 rev 2 when ambmxe = 1, biquad #7 on channe ls 1-6 are utilized for the bass-management crossover filter, this biquad is not user-programmable in this mode. the xo settings determine the crossover frequency used, the crossover is 2 nd order for both high-pass and low-pass with a -3 db cross point. higher order filters can be obtained be programming coefficients in other biquads if desired. it is recommended to use settin gs of 120-160 hz when using small, single driver satellite speakers as the frequency response of these speakers normally is limited to this region. 7.2.34 auto3 - automode am/pre- scale/bass managem ent scale (0x21) bitfield 1 0 fss - front speaker size large small sub - subwoofer on off d7 d6 d5 d4 d3 d2 d1 d0 amam2 amam1 amam0 amame msa amps 0000 00 bit rw rst name description 0rw0 amps automode pre-scale 0: -18 db used for pre-scale when ameq = 00 1: user-defined pre-scale when ameq = 00 bit rw rst name description 1rw0 msa bass management mix scale adjustment 0: -12 db scaling on satellite channels in config #1 1: no scaling on satellite channels in config #1 bit rw rst name description 4rw0 amame automode am enable 0: switching frequency determined by pwms settings 1: switching frequency determined by amam settings amam[2:0] 48 khz/96 khz input fs 44.1 / 88.2 khz input fs 000 0.535 mhz - 0.720 mhz 0.535 mhz - 0.670 mhz 001 0.721 mhz - 0.900 mhz 0.671 mhz - 0.800 mhz 010 0.901 mhz - 1.100 mhz 0.801 mhz - 1.000 mhz 011 1.101 mhz - 1.300 mhz 1.001 mhz - 1.180 mhz 100 1.301 mhz - 1.480 mhz 1.181 mhz - 1.340 mhz 101 1.481 mhz - 1.600 mhz 1.341 mhz - 1.500 mhz 110 1.601 mhz - 1.700 mhz 1.501 mhz - 1.700 mhz
STA309B registers doc id 022570 rev 2 41/66 7.2.35 preeq - pres et eq settings (0x22) d7 d6 d5 d4 d3 d2 d1 d0 xo2 xo1 xo0 peq4 peq3 peq2 peq1 peq0 10100000 xo[2:0] bass management crossover frequency 000 70 hz 001 80 hz 010 90 hz 011 100 hz 100 110 hz 101 120 hz 110 140 hz 111 160 hz peq[4:0] mode / setting 00000 flat 00001 rock 00010 soft rock 00011 jazz 00100 classical 00101 dance 00110 pop 00111 soft 01000 hard 01001 party 01010 vocal 01011 hip-hop 01100 dialog 01101 bass-boost #1 01110 bass-boost #2 01111 bass-boost #3 10000 loudness 1 10001 loudness 2 10010 loudness 3 10011 loudness 4
registers STA309B 42/66 doc id 022570 rev 2 7.2.36 ageq - graphi c eq 80-hz band (0x23) 7.2.37 bgeq - graphi c eq 300-h z band (0x24) 7.2.38 cgeq - graphi c eq 1-khz band (0x25) 7.2.39 dgeq - graphi c eq 3-khz band (0x26) 10100 loudness 5 10101 loudness 6 10110 loudness 7 10111 loudness 8 11000 loudness 9 11001 loudness 10 11010 loudness 11 11011 loudness 12 11100 loudness 13 11101 loudness 14 11110 loudness 15 11111 loudness 16 d7 d6 d5 d4 d3 d2 d1 d0 ageq4 ageq3 ageq2 ageq1 ageq0 01111 d7 d6 d5 d4 d3 d2 d1 d0 bgeq4 bgeq3 bgeq2 bgeq1 bgeq0 01111 d7 d6 d5 d4 d3 d2 d1 d0 cgeq4 cgeq3 cgeq2 cgeq1 cgeq0 01111 d7 d6 d5 d4 d3 d2 d1 d0 dgeq4 dgeq3 dgeq2 dgeq1 dgeq0 01111
STA309B registers doc id 022570 rev 2 43/66 7.2.40 egeq - graphi c eq 8-khz band (0x27) 7.2.41 biquad internal channel loop-through (0x28) each internal processing channel can receive tw o possible inputs at the input to the biquad block. the input can come either from the output of that channel?s mix#1 engine or from the output of the bass/treble (biquad #10) of the previous channel. in this scenario, channel 1 receives channel 8. this enables the use of more than 10 biquads on any given channel at the expense of losing the number of separate internal processing channels. d7 d6 d5 d4 d3 d2 d1 d0 egeq4 egeq3 egeq2 egeq1 egeq0 01111 xgeq[4:0] boost / cut 11111 +16 11110 +15 11101 +14 ?? 10000 +1 01111 0 01110 -1 ?? 00001 -14 00000 -15 d7 d6 d5 d4 d3 d2 d1 d0 c8blp c7blp c6blp c5blp c4blp c3blp c2blp c1blp 00000000 bit rw rst name description 7:0 rw 0 cnblp for n = 1 to 8: 0: input from channel n mix#1 engine output - normal operation 1: input from channel (n - 1) biquad #10 output - loop operation
registers STA309B 44/66 doc id 022570 rev 2 7.2.42 mix internal ch annel loop-through (0x29) each internal processing channel can receive two possible sets of inputs at the inputs to the mix#1 block. the inputs can come from the outputs of the interpolation block as normally occurs (cnmxlp = 0) or they can come from the outputs of the mix#2 block. this enables the use of additional filtering after the second mix block at the expense of losing this processing capability on the channel. 7.2.43 eq bypass (0x2a) eq control can be bypassed on a per-channel basis. if eq control is bypassed on a given channel, the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass management crossover, bass, treble in any combination) are bypassed for that channel. 7.2.44 tone contro l bypass (0x2b) tone control (bass/treble) can be bypassed on a per-channel basis. if tone control is bypassed on a given channel, the two filters that tone control utilizes are made available as user-programmable biquads #9 and #10. d7 d6 d5 d4 d3 d2 d1 d0 c8mxlp c7mxlp c6mxlp c5mxlp c4mxlp c3mxlp c2mxlp c1mxlp 00000000 bit rw rst name description 7:0 rw 0 cnmxlp for n = 1 to 8: 0: inputs to channel n mix #1 engine from interpolation outputs - normal operation 1: inputs to channel n mix #1 engine from mix#2 engine outputs - loop operation d7 d6 d5 d4 d3 d2 d1 d0 c8eqbp c7eqbp c6eqbp c5eqbp c4eqcbp c3eqbp c2eqbp c1eqbp 00000000 bit rw rst name description 7:0 rw 0 cneqbp for n = 1 to 8: 0: perform eq on channel n - normal operation 1: bypass eq on channel n d7 d6 d5 d4 d3 d2 d1 d0 c8tcb c7tcb c6tcb c5tcb c4tcb c3tcb c2tcb c1tcb 00000000
STA309B registers doc id 022570 rev 2 45/66 7.2.45 tone control (0x2c) this is the tone control boost / cut as a function of the btc and ttc bits. 7.2.46 channel limiter sele ct channels 1,2,3,4 (0x2d) 7.2.47 channel limiter sele ct channels 5,6,7,8 (0x2e) 7.2.48 limiter 1 atta ck/release rate (0x2f) d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 01110111 btc[3:0] / ttc[3:0) boost / cut 0000 -12 db 0001 -12 db ?? 0111 -4 db 0110 -2 db 0111 0 db 1000 +2 db 1001 +4 db ?? 1101 +12 db 1110 +12 db 1111 +12db d7 d6 d5 d4 d3 d2 d1 d0 c4ls1 c4ls0 c3ls1 c3ls0 c2ls1 c2ls0 c1ls1 c1ls0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c8ls1 c8ls0 c7ls1 c7ls0 c6ls1 c6ls0 c5ls1 c5ls0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 01101010
registers STA309B 46/66 doc id 022570 rev 2 7.2.49 limiter 1 attack /release threshold (0x30) 7.2.50 limiter 2 atta ck/release rate (0x31) 7.2.51 limiter 2 attack /release threshold (0x32) 7.2.52 bit description the STA309B includes two independent limiter blocks. the purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively redu ce the dynamic range for a better listening environment such as a nighttime listening mode which is often needed for dvds. the two modes are selected via the drc bit in configuration register b, bit 7 address 0x02. each channel can be mapped to either limiter or not mapped, mean ing that the channel will clip when 0 dbfs is exceeded. each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then, if needed, adjust the gain of the mapped channels in unison. the limiter attack thresholds are determined by the lnat registers. it is recommended in anti-clipping mode to set this to 0 dbfs, which corresponds to the maximum unclipped output power of an ffx amplifier. since gain can be added digitally within the STA309B it is possible to exceed 0 dbfs or any other lnat setting. when this occurs, the limiter, when active, will automatically start reducing the gain. the rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. the gain reduction occurs on a peak-detect algorithm. the release of the limiter, when the gain is again increased, is dependent on an rms-detect algorithm. the output of the volume/limiter block is passed through a rms filter. the output of this filter is compared to the release threshold, determined by the release threshold register. when the rms filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register. the gain can never be increased past it's set value and therefore the rele ase will only occur if the limiter has already reduced the gain. the release threshold va lue can be used to set what is effectively a minimum dynamic range which is helpful as overlimiting can reduce the dynamic range to virtually zero and cause program material to sound lifeless. d7 d6 d5 d4 d3 d2 d1 d0 l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 01101001 d7 d6 d5 d4 d3 d2 d1 d0 l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 01101010 d7 d6 d5 d4 d3 d2 d1 d0 l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 01101001
STA309B registers doc id 022570 rev 2 47/66 in ac mode the attack and release thresholds are set relative to full-scale. in drc mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting, plus the attack threshold. figure 7. basic limiter and volume flow diagram cnls[1,0] channel limiter mapping 00 channel has limiting disabled 01 channel is mapped to limiter #1 10 channel is mapped to limiter #2 lna[3:0] attack rate (db/ms) 0000 3.1584 (fast) 0001 2.7072 0010 2.2560 0011 1.8048 0100 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 1000 0.1504 1001 0.1123 1010 0.0902 1011 0.0752 1100 0.0645 1101 0.0564 1110 0.0501 1111 0.0451 (slow) g a in atten ua tion sa t u r a tion rm s limiter g a in/vol u me t u p t u o t u p n i
registers STA309B 48/66 doc id 022570 rev 2 lnr[3:0] release rate (db/ms) 0000 0.5116 (fast) 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 1111 0.0104 (slow) lnat[3:0] anti-clipping (ac) (db relative to f s ) 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 +8 1110 +9 1111 +10
STA309B registers doc id 022570 rev 2 49/66 lnrt[3:0] anti-clipping (ac) (db relative to f s ) 0000 - 0001 -29 db 0010 -20 db 0011 -16 db 0100 -14 db 0101 -12 db 0110 -10 db 0111 -8 db 1000 -7 db 1001 -6 db 1010 -5 db 1011 -4 db 1100 -3 db 1101 -2 db 1110 -1 db 1111 -0 db lnat[3:0] dynamic range compression (drc) (db relative to volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4
registers STA309B 50/66 doc id 022570 rev 2 7.2.53 channel 1 and 2 output timing (0x33) 7.2.54 channel 3 and 4 output timing (0x34) 7.2.55 channel 5 and 6 output timing (0x35) lnrt[3:0] dynamic range compression (drc) (db relative to volume + lnat) 0000 - 0001 -38 db 0010 -36 db 0011 -33 db 0100 -31 db 0101 -30 db 0110 -28 db 0111 -26 db 1000 -24 db 1001 -22 db 1010 -20 db 1011 -18 db 1100 -15 db 1101 -12 db 1110 -9 db 1111 -6 db d7 d6 d5 d4 d3 d2 d1 d0 c2ot2 c2ot1 c2ot0 c1ot2 c1ot1 c1ot0 100 000 d7 d6 d5 d4 d3 d2 d1 d0 c4ot2 c4ot1 c4ot0 c3ot2 c3ot1 c3ot0 110 010 d7 d6 d5 d4 d3 d2 d1 d0 c6ot2 c6ot1 c6ot0 c5ot2 c5ot1 c5ot0 101 001
STA309B registers doc id 022570 rev 2 51/66 7.2.56 channel 7 and 8 output timing (0x36) the centering of the individual channel pwm output periods can be adjusted by the output timing registers. the pwm slot settings can be chosen to ensure that pulse transitions do not occur at the same time on different channels using the same power device. there are 8 possible settings, the appropriate setting is based on the application and connections to the ffx power devices. 7.2.57 channel i 2 s output mapping ch annels 1 and 2 (0x37) 7.2.58 channel i 2 s output mapping ch annels 3 and 4 (0x38) 7.2.59 channel i 2 s output mapping ch annels 5 and 6 (0x39) d7 d6 d5 d4 d3 d2 d1 d0 c8ot2 c8ot1 c8ot0 c7ot2 c7ot1 c7ot0 111 011 cnot[2:0] pwm slot 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 d7 d6 d5 d4 d3 d2 d1 d0 c2om2 c2om1 c2om0 c1om2 c1om1 c1om0 001 000 d7 d6 d5 d4 d3 d2 d1 d0 c4om2 c4om1 c4om0 c3om2 c3om1 c3om0 011 010 d7 d6 d5 d4 d3 d2 d1 d0 c6om2 c6om1 c6om0 c5om2 c5om1 c5om0 101 100
registers STA309B 52/66 doc id 022570 rev 2 7.2.60 channel i 2 s output mapping ch annels 7 and 8 (0x3a) each i 2 s output channel can receive data from any channel output of the volume block. which channel a particular i 2 s output receives is dependent upon that channel?s cnom register bits. 7.2.61 coefficient addr ess register 1 (0x3b) 7.2.62 coefficient addr ess register 2 (0x3c) 7.2.63 coefficient b1 data register, bits 23:16 (0x3d) d7 d6 d5 d4 d3 d2 d1 d0 c8om2 c8m1 c8om0 c7om2 c7om1 c7om0 111 110 cnom[2:0] serial output from 000 channel 1 001 channel 2 010 channel 3 011 channel 4 100 channel 5 101 channel 6 110 channel 7 111 channel 8 d7 d6 d5 d4 d3 d2 d1 d0 cfa9 cfa8 00 d7 d6 d5 d4 d3 d2 d1 d0 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000
STA309B registers doc id 022570 rev 2 53/66 7.2.64 coefficient b1 data register, bits 15:8 (0x3e) 7.2.65 coefficient b1 data register, bits 7:0 (0x3f) 7.2.66 coefficient b2 data register, bits 23:16 (0x40) 7.2.67 coefficient b2 data register, bits 15:8 (0x41) 7.2.68 coefficient b2 data register, bits 7:0 (0x42) 7.2.69 coefficient a1 data register, bits 23:16 (0x43) 7.2.70 coefficient a1 data register, bits 15:8 (0x44) d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 00000000
registers STA309B 54/66 doc id 022570 rev 2 7.2.71 coefficient a1 data register, bits 7:0 (0x45) 7.2.72 coefficient a2 data register, bits 23:16 (0x46) 7.2.73 coefficient a2 data register, bits 15:8 (0x47) 7.2.74 coefficient a2 data register, bits 7:0 (0x48) 7.2.75 coefficient b0 data register, bits 23:16 (0x49) 7.2.76 coefficient b0 data register, bits 15:8 (0x4a) 7.2.77 coefficient b0 data register, bits 7:0 (0x4b) d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 00000000
STA309B registers doc id 022570 rev 2 55/66 7.2.78 coefficient write control register (0x4c) coefficients for eq and bass management are handled internally in the STA309B via ram. access to this ram is available to the user via an i 2 c register interface. a collection of i 2 c registers are dedicated to this func tion. one contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write of the coefficient(s) to ram. the following are instructions for re ading and writing coefficients. 7.3 reading a coefficient from ram 1. write top 2 bits of address to i 2 c register 0x3b 2. write bottom 8 bits of address to i 2 c register 0x3c 3. read top 8 bits of coefficient in i 2 c address 0x3d 4. read middle 8 bits of coefficient in i 2 c address 0x3e 5. read bottom 8 bits of coefficient in i 2 c address 0x3f 7.4 reading a set of coefficients from ram 1. write top 2 bits of address to i 2 c register 0x3b 2. write bottom 8 bits of address to i 2 c register 0x3c 3. read top 8 bits of coefficient in i 2 c address 0x3d 4. read middle 8 bits of coefficient in i 2 c address 0x3e 5. read bottom 8 bits of coefficient in i 2 c address 0x3f 6. read top 8 bits of coefficient b2 in i 2 c address 0x40 7. read middle 8 bits of coefficient b2 in i 2 c address 0x41 8. read bottom 8 bits of coefficient b2 in i 2 c address 0x42 9. read top 8 bits of coefficient a1 in i 2 c address 0x43 10. read middle 8 bits of coefficient a1 in i 2 c address 0x44 11. read bottom 8 bits of coefficient a1 in i 2 c address 0x45 12. read top 8 bits of coefficient a2 in i 2 c address 0x46 13. read middle 8 bits of coefficient a2 in i 2 c address 0x47 14. read bottom 8 bits of coefficient a2 in i 2 c address 0x48 15. read top 8 bits of coefficient b0 in i 2 c address 0x49 16. read middle 8 bits of coefficient b0 in i 2 c address 0x4a 17. read bottom 8 bits of coefficient b0 in i 2 c address 0x4b d7 d6 d5 d4 d3 d2 d1 d0 wa w1 00
registers STA309B 56/66 doc id 022570 rev 2 7.5 writing a single coefficient to ram 1. write top 2 bits of address to i 2 c register 0x3b 2. write bottom 8 bits of address to i 2 c register 0x3c 3. write top 8 bits of coefficient in i 2 c address 0x3d 4. write middle 8 bits of coefficient in i 2 c address 0x3e 5. write bottom 8 bits of coefficient in i 2 c address 0x3f 6. write 1 to w1 bit in i 2 c address 0x4c 7.6 writing a set of coefficients to ram 1. write top 2 bits of starting address to i 2 c register 0x3b 2. write bottom 8 bits of starting address to i 2 c register 0x3c 3. write top 8 bits of coefficient b1 in i 2 c address 0x3d 4. write middle 8 bits of coefficient b1 in i 2 c address 0x3e 5. write bottom 8 bits of coefficient b1 in i 2 c address 0x3f 6. write top 8 bits of coefficient b2 in i 2 c address 0x40 7. write middle 8 bits of coefficient b2 in i 2 c address 0x41 8. write bottom 8 bits of coefficient b2 in i 2 c address 0x42 9. write top 8 bits of coefficient a1 in i 2 c address 0x43 10. write middle 8 bits of coefficient a1 in i 2 c address 0x44 11. write bottom 8 bits of coefficient a1 in i 2 c address 0x45 12. write top 8 bits of coefficient a2 in i 2 c address 0x46 13. write middle 8 bits of coefficient a2 in i 2 c address 0x47 14. write bottom 8 bits of coefficient a2 in i 2 c address 0x48 15. write top 8 bits of coefficient b0 in i 2 c address 0x49 16. write middle 8 bits of coefficient b0 in i 2 c address 0x4a 17. write bottom 8 bits of coefficient b0 in i 2 c address 0x4b 18. write 1 to wa bit in i 2 c address 0x4c the mechanism for writing a set of coefficients to ram provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. when using this technique, the 10-bit address specifies the address of the biquad b1 coefficient (for example, decimals 0, 5, 10, 15, ?, 100, ? 395), and the STA309B generates the ram addresses as offsets from this base value to write the complete set of coefficient data.
STA309B equalization and mixing doc id 022570 rev 2 57/66 8 equalization and mixing figure 8. channel mixer 8.1 post-scale the STA309B provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. this is a 24-bit signed fractional multiplier. the scale factor for this multiplier is loaded into ram using the same i 2 c registers as the biquad coefficients and the bass-management. this post-scale factor can be used in conjunc tion with an adc-equipped microcontroller to perform power-supply error correction. all channels can use channel 1 by setting the post- scale link bit. channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 cxmix1 cxmix2 cxmix3 cxmix4 cxmix5 cxmix6 cxmix7 cxmix8 channel x table 9. ram block for biquads, mixing, and bass management index (decimal) index (hex) coefficient default 0 0x00 channel 1 - biquad 1 c1h10 (b1/2) 0x000000 1 0x01 c1h11 (b2) 0x000000 2 0x02 c1h12 (a1/2) 0x000000 3 0x03 c1h13 (a2) 0x000000 4 0x04 c1h14 (b0/2) 0x400000 5 0x05 channel 1 - biquad 2 c1h20 0x000000
equalization and mixing STA309B 58/66 doc id 022570 rev 2 ??? ? ? 49 0x31 channel 1 - biquad 10 c1ha4 0x400000 50 0x32 channel 2 - biquad 1 c2h10 0x000000 51 0x33 c2h11 0x000000 ??? ? ? 99 0x63 channel 2 - biquad 10 c2ha4 0x4000000 100 0x64 channel 3 - biquad 1 c3h10 0x000000 ??? ? ? 399 0x18f channel 8 - biquad 10 c8ha4 0x400000 400 0x190 channel 1 - pre-scale c1pres 0x7fffff 401 0x191 channel 2 - pre-scale c2pres 0x7fffff 402 0x192 channel 3 - pre-scale c3pres 0x7fffff ??? ? ? 407 0x197 channel 8 - pre-scale c8pres 0x7fffff 408 0x198 channel 1 - post-scale c1psts 0x7fffff 409 0x199 channel 2 - post-scale c2psts 0x7fffff ??? ? ? 415 0x19f channel 8 - post-scale c8psts 0x7fffff 416 0x1a0 channel 1 - mix#1 1 c1mx11 0x7fffff 417 0x1a1 channel 1 - mix#1 2 c1mx12 0x000000 ??? ? ? 423 0x1a7 channel 1 - mix#1 8 c1mx18 0x000000 424 0x1a8 channel 2 - mix#1 1 c2mx11 0x000000 425 0x1a9 channel 2 - mix#1 2 c2mx12 0x7fffff ??? ? ? 463 0x1cf channel 8 - mix#1 8 c8mx18 0x7fffff 464 0x1d0 channel 1 - mix#2 1 c1mx21 0x7fffff 465 0x1d1 channel 1 - mix#2 2 c1mx22 0x000000 ??? ? ? 471 0x1d7 channel 1 - mix#2 8 c1mx28 0x000000 472 0x1d8 channel 2 - mix#2 1 c2mx21 0x000000 473 0x1d9 channel 2 - mix#2 2 c2mx22 0x7fffff ??? ? ? 527 0x20f channel 8 - mix#2 8 c8mx28 0x7fffff table 9. ram block for biquads, mixing, and bass management (continued) index (decimal) index (hex) coefficient default
STA309B equalization and mixing doc id 022570 rev 2 59/66 8.2 variable maximum power correction 8.2.1 mpcc1-2 (0x4d, 0x4e) the mpcc bits determine the 16 msbs of the mpc compensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. 8.3 variable distortion compensation 8.3.1 dcc1-2 (0x4f, 0x50) the dcc bits determine the 16 msbs of the distortion compensation coefficient. this coefficient is used in place of th e default coefficient when dccv = 1. d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 00101101 d7 d6 d5 d4 d3 d2 d1 d0 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 11110011 d7 d6 d5 d4 d3 d2 d1 d0 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 00110011
equalization and mixing STA309B 60/66 doc id 022570 rev 2 8.4 pscorrect registers adc is used to input ripple data to sdi78. the left channel (7) is used internally. no audio data can therefore be used on these channels, although all channel mapping and mixing from other inputs to channels 7 and 8 internally are still valid. 8.4.1 psc1-2: ripple correct ion value (rcv) (0x51, 0x52) this function is equivalent to the negative maximum ripple peak as a percentage of vcc (mpr), scaled by the inverse of the maximum ripple p-p as a percentage of full-scale analog input to adc. it is represented as a 1.11 signed fractional number. 8.4.2 psc3: correction normali zation value (cnv) (0x53) this function is equivalent to 1 / (1+mpr) expressed as a 0.12 unsigned fractional number. 8.5 digital pop-free operat ion in single-ended mode the STA309B pop-free feature allows digitally pre-loading the bypass capacitor between the filtered amplifier output and the load in single-ended applications. normally, a bypass capacitor needs to be preloaded to half of the power supply in order to avoid having pop- noise at pwm startup. by enabling the STA309B pop-free feature, it is possible to preload the capacitor using the amplifier, without needing the resistive partition. by forcing a ramp, it is possible to gradually load the capacitor from zero to half the supply with the pwm signal starting from near 0% duty cycle to 50% duty cycle. this ?active load? is also faster than the resistive partition method. d7 d6 d5 d4 d3 d2 d1 d0 rcv11 rcv10 rcv9 rcv8 rcv7 rcv6 rcv5 rcv4 00000000 d7 d6 d5 d4 d3 d2 d1 d0 rcv3 rcv2 rcv1 rcv0 cnv11 cnv10 cnv9 cnv8 00001111 d7 d6 d5 d4 d3 d2 d1 d0 cnv7 cnv6 cnv5 cnv4 cnv3 cnv2 cnv1 cnv0 11111111
STA309B equalization and mixing doc id 022570 rev 2 61/66 figure 9. typical single-ended driver - power stage configuration the r pull-down resistor (typical value: 3.3 kohm) is placed to ensure that there is zero voltage across the load and the bypass capacitor is discharged when the amplifier is in tristate mode. 8.5.1 pfcxon: digital pop-free register (0x5f) pfcxon[i]: when ?1?, digital pop free is active on channel i+1 when in binary mode (see section 7.2.5: configuration register e (0x04) on page 28 ) when ?0?, digital pop free is not active on channel i+1 8.5.2 timing settings figure 10. pop-free timing diagram STA309B sta5xx y x t u o y x t u o eapd tri-state inxy cbyp pwrdn STA309B sta5xx y x t u o y x t u o eapd tri-state inxy cbyp pwrdn STA309B sta5xx y x t u o y x t u o eapd tri-state inxy cbyp pwrdn d7 d6 d5 d4 d3 d2 d1 d0 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 11111111 ? eapd out gnd vcc/2 l s pdwt t s pupt ramptim ramptim ? eapd out gnd vcc/2 l s pdwt t s pupt ramptim ramptim
equalization and mixing STA309B 62/66 doc id 022570 rev 2 8.5.3 ramptim: ramp dur ation register (0x66) this function is the total pop-free ramp duration (same value for ramp-up and ramp-down and for all channels); default is 400 ms (range is 0-25 sec.). 8.5.4 tspupt: waiting ti me after eapd (0x67 - 0x68) this function is the waitin g time after eapd=1 to start ramp-up (same value for all channels); default is 680 ms (range is 0-11 sec.). in a ty pical application the eapd line is connected to the tri-state input pin of the sta5xx power stage through the rc filter (see figure 9 on page 61 ). tspupt shall be greater than the rc time constant. 8.5.5 lspdwt: waiting ti me before eapd (0x71 - 0x72) this function is the waiting time after end of ramp-down to assert eapd=0 (same value for all channels); default is 1.4 sec. (range is 0-11 sec.). if a resistor is placed in parallel to the output filter capacitor (see figure 9 on page 61 ), the lspdwt value is 0x00. d7 d6 d5 d4 d3 d2 d1 d0 tr7 tr6 tr5 tr4 tr3 tr2 tr1 tr0 00000100 d7 d6 d5 d4 d3 d2 d1 d0 tp15 tp14 tp13 tp12 tp11 tp10 tp9 tp8 00010000 d7 d6 d5 d4 d3 d2 d1 d0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 tl15 tl14 tlp13 tl12 tl11 tl10 tl9 tl8 00100000 d7 d6 d5 d4 d3 d2 d1 d0 tl7 tl6 tl5 tl4 tl3 tl2 tl1 tl0 00000000
STA309B package information doc id 022570 rev 2 63/66 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 10. vfqfpn-56 (8 x 8 mm) package dimensions reference mm min. typ. max. a 0.80 0.90 1.00 a1 0 0.05 d8.00 d2 see exposed pad variations e8.00 e2 see exposed pad variations b 0.25 0.30 0.35 b1 0.20 0.25 0.30 e (pad pitch) (1) 1. refer to figure 11 . l1 0.05 0.15 aaa 0.15 bbb 0.10 ddd 0.05 eee 0.08 fff 0.10 ccc 0.10 table 11. exposed pad variations variation d2 e2 min. typ. max min. typ. max. a 5.85 5.90 5.95 5.85 5.90 5.95 b 4.25 4.30 4.35 4.25 4.30 4.35
package information STA309B 64/66 doc id 022570 rev 2 figure 11. vfqfpn-56 (8 x 8 mm) package outline the axis of each pad must lie simultaneously in both tolerance zones. (4) - the terminal a1 corner must be identified on the top surface through inked or lasered mark dot. a distinguishing feature is allowable on the bottom su rface of the package, chamfer at die paddle corner to identify the terminal a1. exact shape of each corner is optional. (5) ? all dimensions are in mm. 8 26 8 20
STA309B revision history doc id 022570 rev 2 65/66 10 revision history table 12. document revision history date revision changes 09-dec-2011 1 initial release 24-jan-2012 2 updated title and description on page 1
STA309B 66/66 doc id 022570 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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